In the fabrication of semiconductor devices such as integrated circuits, memory cells, and the like, a series of manufacturing operations are performed to define features on semiconductor wafers (“wafers”). The wafers (or substrates) include integrated circuit devices in the form of multi-level structures defined on a silicon substrate. At a substrate level, transistor devices with diffusion regions are formed. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistor devices to define a desired integrated circuit device. Also, patterned conductive layers are insulated from other conductive layers by dielectric materials.
During the series of manufacturing operations, the wafer surface is exposed to various types of contaminants. Essentially any material present in a manufacturing operation is a potential source of contamination. For example, sources of contamination may include process gases, chemicals, deposition materials, and liquids, among others. The various contaminants may deposit on the wafer surface in particulate form. If the particulate contamination is not removed, the devices within the vicinity of the contamination will likely be inoperable. Thus, it is necessary to clean contaminants from the wafer surface in a substantially complete manner without damaging the features defined on the wafer. However, the size of particulate contamination is often on the order of the critical dimension size of features fabricated on the wafer. Removal of such small particulate contamination without adversely affecting the features on the wafer can be quite difficult.